FIG. 5 shows an example of conventional semiconductor light emitting device. The semiconductor light emitting device X shown in the figure includes an n-GaN layer 92 which is an n-type semiconductor layer formed on a substrate 91, a p-GaN layer 93 which is a p-type semiconductor layer, and an active layer 94 having a multiple quantum well (hereinafter referred to as “MQW”) structure. The active layer 94 has a laminated structure made up of semiconductor layers containing InGaN with different In composition ratios. An n-side electrode 95 is formed on the lower surface (in FIG. 5) of the substrate 91, whereas a p-side electrode 96 is formed on an upper surface (in FIG. 5) of the p-GaN layer 93. The active layer 94 is sandwiched between lower clad layers 97a, 97b and upper clad layers 98a, 98b. The lower clad layer 97a and the upper clad layer 98a are semiconductor layers containing InGaN and having the same In composition ratio as that of the barrier layer of the active layer 94. Thus, the lower clad layers 97a, 97b and the upper clad layers 98a, 98b alleviate the lattice strain between the layers sandwiching the clad layers.
Each of the layers constituting the semiconductor light emitting device X is very thin, having a thickness of several tens of nanometers. Thus, it is difficult to control the In composition ratio in the manufacturing process. For instance, in forming the upper clad layer 98b after the upper clad layer 98a is formed, the In contained in the upper clad layer 98a may be lost by sublimation due to difference between these layers in formation temperature or formation gas, for example. In such a case, the In composition ratio in the upper clad layer 98a unduly reduces, whereby the alleviation of the lattice strain between the active layer 94 and the p-GaN layer 93 is hindered.    Patent Document 1: JP-A-2005-150627